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The LXT305A receives the signal input from one twistedpair line on each side of a center-grounded transformer. Positive pulses are received at RTIP and negative pulses are received at RRING. Recovered data is output at RPOS and RNEG, and the recovered clock is output at RCLK. Refer to Test Specifications for LXT305A receiver timing. The signal received at RPOS and RNEG is processed through the peak detector and data slicers. The peak detector samples the inputs and determines the maximum value of the received signal. A percentage of the peak value is provided to the data slicers as a threshold level to ensure optimum signal-to-noise ratio. For T1 applications (determined by Equalizer Control inputs EC1 - EC3 000 or 001) the threshold is set to 70% of the peak value. This threshold is maintained above 65% for up to 15 successive zeros over the range of specified operating conditions. For E1 applications (EC inputs = 000 or 001) the threshold is 50%. The receiver is capable of accurately recovering signals with up to -13.6 dB of attenuation (from 2.4 V), corresponding to a received signal level of approximately 500 mV. Maximum line length is 1500 feet of ABAM cable (approximately 6 dB of attenuation). Regardless of received signal level, the peak detectors are held above a minimum level of .3 V to provide immunity from impulsive noise. After processing through the data slicers, the received signal is routed to the data and clock recovery sections, and to the receive monitor. The data and clock recovery circuits are highly tolerant with an input jitter tolerance significantly better than required by Pub 62411. Refer to Test Specifications for additional information. The receiver monitor loads a digital counter at the RCLK frequency. The count is incremented each time a zero is received, and reset to zero each time a one (mark) is received. Upon receipt of 175 consecutive zeros the LOS pin goes High, and a smooth transition replaces the RCLK output with the MCLK. Received marks are output regardless of the LOS status, but the LOS pin will not reset until the ones density reaches 12.5%. This level is based on receipt of at least 4 ones in any 32-bit period with no more than 15 consecutive zeros.
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Data received for transmission onto the line is clocked serially into the device at TPOS and TNEG. Input synchronization is supplied by the transmit clock (TCLK). The transmitted pulse shape is determined by Equalizer Control signals EC1 through EC3 as shown in Table 4. Refer to Test Specifications for master and transmit clock timing characteristics. Shaped pulses are applied to the AMI line driver for transmission onto the line at TTIP and TRING. Equalizer Control signals may be hardwired in the Hardware Mode, or input as part of the serial data stream (SDI) in the Host Mode Pulses can be shaped for either 1.544 or 2.048 Mbps applications. 1.544 Mbps pulses for DSX-1 applications can be programmed to match line lengths from 0 to 655 feet of ABAM cable. The LXT305A also matches FCC and ECSA specifications for CSU applications. 2.048 Mbps pulses can drive coaxial or shielded twisted-pair lines.
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Jitter attenuation of the LXT305A transmit outputs is provided by a Jitter Attenuation Loop (JAL) and an Elastic Store (ES). An external crystal oscillating at 4 times the bit rate provides clock stabilization. Refer to Application Information for crystal specifications. The ES is a 32 x 2bit register. Transmit data is clocked into the ES with the transmit clock (TCLK) signal, and clocked out of the ES with the dejittered clock from the JAL. When the bit count in the ES is within two bits of overflowing or underflowing, the ES adjusts the output clock by 1/8 of a bit period. The ES produces an average delay of 16 bits in the receive path.
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The LXT305A transmits data as a 50% AMI line code as shown in Figure 2. The output driver maintains a constant low output impedance regardless of whether it is driving marks or spaces. This well controlled output impedance provides excellent return loss (> 18 dB) when used with external 9.1 precision ( 1 % accuracy) in series with a transmit transformer with a turns ratio of 1:2.3 ( 2% accu-
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The LXT305A serial port is addressed by setting bit A4 in the Address/Command byte, corresponding to address 16. The LXT305A contains only a single output data register so no complex chip addressing scheme is required. The register is accessed by causing the Chip Select (CS) input to transition from High to Low. Bit 1 of the serial Address/ Command byte provides Read/Write control when the chip is accessed. A logic 1 indicates a read operation, and a logic 0 indicates a write operation. Table 2 lists serial data output bit combinations for each status. Serial data I/O timing characteristics are shown in the Test Specifications section.
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1. Transformer turns ratio accuracy is 2%. 2. Rr and Rt values are 1%. 3. Typical return loss, 51 kHz to 3.072 MHz band.
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